SPI Lab

SPI Tunnel Controller

SPI across a link, for example a SerDes SPI bridge, handled in hardware.

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Overview

The SPI Tunnel Controller carries SPI transactions across a link, for example the SPI bridge of a SerDes. It runs the bridge protocol in logic: handshake, subordinate-select control commands, stale-buffer drain and timeout with safe release of the remote select. Commands are 1 to 15 bytes. The local bus is fixed to SPI mode 0, as the bridge requires.

Features

  • Bridge protocol in logic: handshake and subordinate-select control commands
  • Stale-buffer drain
  • 1–15-byte commands
  • Timeout with safe release of the remote select
  • Debug state output
  • Local bus fixed to SPI mode 0, as the bridge requires
  • Single clock domain; synchronous active-high reset; std_logic-only ports; no vendor primitives
  • Self-checking testbenches included

Block diagram

SPI Tunnel Controller block diagramHost commands of 1 to 15 bytes enter a command engine that runs the bridge handshake, subordinate-select commands, stale-buffer drain and timeout. It returns response bytes, busy and timeout status, and a debug state output. The engine drives a local SPI main fixed to mode 0, which connects to an external SerDes SPI bridge.spi_tunnelcommand, 1–15 bytesresponse bytesbusy / timeoutdebug stateCommand enginebridge handshake,select commands,drain, timeoutLocal SPI mainmode 0 (fixed)SCLKMOSIMISOCS_NSerDesSPI bridgeexternal
Fig. 1 SPI Tunnel Controller, functional view. The SerDes SPI bridge is outside the core. clk and rst not drawn.

Specifications

ParameterValue
HDLVHDL, synthesizable
Clock domains1 (fclk)
ResetSynchronous, active-high
SPI mode0 (fixed)
Command length1–15 bytes
ProtocolBridge handshake, select commands, stale-buffer drain
TimeoutSafe release of the remote select
DebugState output
Port typesstd_logic only
Vendor primitivesNone
VerificationSelf-checking testbenches

Interface

PortDirWidthDescription
clkin1System clock, fclk
rstin1Synchronous reset, active-high
cmd_datain8Command byte
cmd_lenin4Command length, 1–15
cmd_startin1Start a command
rsp_dataout8Response byte
rsp_validout1Response byte valid
busyout1Command in progress
timeoutout1Timeout occurred
dbg_stateoutnDebug state
sclkout1SPI clock to bridge
cs_nout1Chip select, active low
mosiout1Data to bridge
misoin1Data from bridge
Port list for orientation; the datasheet is authoritative. W = word width generic.

Performance

Throughput depends on the bridge and link configuration. Figures for your setup: ask sales.

Resource utilisation

DeviceLUTsFFsFmax
AMD 7 SeriesPublished after synthesis — ask sales
Altera CyclonePublished after synthesis — ask sales
Lattice ECP5Published after synthesis — ask sales

Supported targets

Vendor-neutral VHDL with no vendor primitives or constraints. The source licence targets any family listed under supported FPGA vendors, including NI LabVIEW FPGA targets through the IP Integration Node. An evaluation netlist is built for one named device and toolchain version.

Deliverables

ItemEvaluationSource licence
Delivered asNetlist for one named device + toolchainVHDL source + testbenches
DocumentationDatasheetDatasheet, integration guide, testbench guide
UseEvaluation only, [terms to fill in]Production, [terms to fill in]
Full terms: Licensing & evaluation.

Documentation

DocumentFormatAvailability
SPI Tunnel Controller — DatasheetPDFPublic
Integration guidePDFWith source licence
Testbench guidePDFWith source licence
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