Overview The SPI Main Frame core is the SPI Main core plus a frame sequencer. One trigger sends N words under a single chip select. A valid/request stream handshake connects it directly to a FIFO, and frame-wide busy and done signals report progress. The host design needs no glue logic.
Features
SPI Main core plus frame sequencer
One trigger sends N words under a single CS
Valid/request stream handshake for FIFOs
Frame-wide busy and done
No glue logic in the host design
Inherits SPI Main: modes 0–3 at runtime, 16-bit divider, 8/16/32-bit words, MSB first, double-registered MISO
Single clock domain; synchronous active-high reset; std_logic -only ports; no vendor primitives
Self-checking testbenches included
Block diagram
Fig. 1 SPI Main Frame core, functional view. clk and rst not drawn. Specifications
Parameter Value
HDL VHDL, synthesizable Clock domains 1 (fclk ) Reset Synchronous, active-high SPI modes 0, 1, 2, 3; CPOL /CPHA at runtime Bit order MSB first Word width 8, 16 or 32 bits (generic) SCLK divider 16-bit; SCLK = fclk / (2·(div+1)) Frames N words per trigger under one chip select Host interface Valid/request stream handshake; frame busy and done Port types std_logic onlyVendor primitives None Verification Self-checking testbenches
Interface
Port Dir Width Description
clk in 1 System clock, fclk rst in 1 Synchronous reset, active-high cpol in 1 Clock polarity cpha in 1 Clock phase clk_div in 16 SCLK divider value trigger in 1 Start a frame n_words in N Words in the frame tx_data in W Stream data tx_valid in 1 Stream data valid tx_req out 1 Request next word rx_data out W Word received busy out 1 Frame in progress done out 1 Frame complete sclk out 1 SPI clock cs_n out 1 Chip select, active low mosi out 1 Main out, subordinate in miso in 1 Main in, subordinate out Port list for orientation; the datasheet is authoritative. W = word width generic.
Supported targets
Vendor-neutral VHDL with no vendor primitives or constraints. The source licence targets any family listed under supported FPGA vendors , including NI LabVIEW FPGA targets through the IP Integration Node. An evaluation netlist is built for one named device and toolchain version.
Deliverables
Item Evaluation Source licence
Delivered as Netlist for one named device + toolchain VHDL source + testbenches Documentation Datasheet Datasheet, integration guide, testbench guide Use Evaluation only, [terms to fill in] Production, [terms to fill in] Full terms: Licensing & evaluation .